The present invention relates to a data error correction circuit for detecting and correcting data errors occurring during data transfer.
Recently, with the increase of the memory density of a magnetic disk memory, the probability of data errors occurring during data transfer has also increased. For example, a burst error or a series of erroneous bits caused by, for example, defects in storage media or external electric noise in the data to be transferred can seriously affect a data processing system. Conventionally, in order to solve these problems, various data error correction circuits have been provided for detecting and correcting data errors. For example, a data error correction circuit utilizing Fire codes is extremely effective in correcting a burst error. When correcting erroneous data using the Fire codes, the maximum number of bits and the number of correctable bits are determined according to a generator polynomial selected from a plurality of generator polynomials for generating fire codes in order to calculate check bits. When the number of check bits is 32, and the generator polynomial G(x) is (x.sup.21 +1)(x.sup.11 +x.sup.2 +1), the maximum number of transferrable bits (the length of a Fire code) and the number of correctable bits are set to 42,987 and 11, respectively.
Usually, for detecting and correcting an error in data to be transferred, the data is divided into units each of which corresponds to a predetermined number of bits, and a check bit is generated according to each unit of serial data. Each check bit is obtained in the form of a remainder obtained by dividing each unit serial data by the generator polynomial G(x) in terms of the modulo 2. Each check bit or remainder thus obtained is added to the end of the corresponding serial data and stored in a memory such as a magnetic disk memory. When transferring data from this memory, the unit serial data is read out together with the check bit, and a sequence data including the unit serial data and the check bit are divided by the generator polynomial G(x). The remainder of the division operation represents a bit pattern known as a syndrome. If the unit serial data read out from the memory does not include an error, the syndrome becomes 0. Thus, when the syndrome is not 0, it indicates occurrence of an error. At this time, the position and the content of the erroneous bit in the unit serial data can be obtained by checking the bit position at which "1" is generated. Conventionally, a data error correction circuit is provided wherein a burst error can be corrected by calculating an exclusive OR product of a sequence of data including a burst error, and an error pattern obtained by cyclically shifting the syndrome. However, this data error correction circuit presents a problem in actual detection and the correction of an error occurring in data to be transferred. That is, even if the maximum number of bits of transferrable data is set to 42,987, the data to be actually transferred is of, for example, 128, 256, 512 or 1024 bytes. Therefore, unnecessary data may be generated. For example, data to be transferred of 1024 bytes or 8192 bits corresponds to about 1/5 of the maximum transferrable number of bits (42,987). Thus, upon the error detection and correction operation, data of about 35,000 bits may be transferred with no purpose, thus reducing the efficiency of the error correction circuit.
In order to overcome the above drawbacks, a method such as the Chinese remainder theorem method is provided for correcting errors at a high speed. However, this method requires a more complicated circuit configuration. Another data error correction circuit is also provided which shortens the length of data to be transferred or processed. However, if the length of the shortened data is set, it cannot be changed. In order to change the length of data, the configuration of the data error correction circuit itself must be altered.